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1 4407a?scr?04/05 features contactless interface ? reads and writes passive rfid tags in the unlicensed 13.56 mhz band ? employs iso/iec14443 type a modulation schemes ? autonomous operation capability (can scan and read tags without host intervention ? i.e. only passes data following successful read/write operation) ? compatible with nfc initiation only device ? user has control over initiation of all rfid based services and features ? read/write operation between 1 cm and 10 cm read range, depending on reader/tag antenna coil sizes and orientation relative to the reader ? collision detection as standard ? transparent modes for software controlled modulation supports maximum flexibility and future protocols ? fast data communication rate of 106 kbit/s ? suitable for operation with a wide variety of antenna coil sizes and form factors ? four software adjustable carrier field drive levels controller and software ? on-board powerful atmel avr ? risc microcontroler, programmed with innovision ? proprietary software. ? built in self test and diagnostic modes ? internal 8 mhz rc oscillator for micro or external crystal operation host interface ? 3-wire spi interface as standard ? full software control via spi bus at 115 kbaud as standard interface power supply ? ultra low current operation and stand-by sleep mode typically < 1 a ? ultra low voltage operation: 2.7v - 3.3v additional features ? packages: lbga36 ? lbga requires only an external crystal, 10 passives and the reader antenna coil ? operating temperature range: -30c to +80c description AT90RF135602 is an ultra small footprint low-cost radio frequency identification (rfid) reader developed with innovision research & technology plc to address multi-protocol 13.56 mhz rfid applications. it is optimised for use with the established iso/iec14443 type a standard and is avail- able in low-profile ball grid array (lbga). the lbga incorporates a custom transceiver front-end along with a protocol & com- munications controller. it requires only an external crystal and minimal external passive components to interface to the reader antenna. protocols are software defined and hence configurable. integrated 13.56 mhz contactless reader with embeded software AT90RF135602
2 4407a?scr?04/05 benefits low-cost ? ideal for rfid applications where costs have traditionally proved prohibitive ultra miniature footprint for compact reader design low voltage operation ideal for rechargeable and/or portable applications low operating current for optimal power utilisation low quiescent current sleep mode further prolongs battery life of applications easily integrated into host reader system scalable on-board processor memory size and capacity for custom design solutions operation with multiple protocols such as philips mifare ? ultralight, innovision ? -r&t jewel ? and iso/iec14443 type a tags ensures multi-platform compatibility and seamless integration into legacy systems software performs mapping between a common logical memory structure model and physical memory maps of multiple tags types also operates with innovision r&t proprietary protocols and transparent reader modes for even lower power consumption levels powerful on board risc processor is available to operate at higher levels of application protocol stack than on conventional reader solutions for more autonomous modes of operation applications passive read/write rfid tag applications operating in the unlicensed 13.56 mhz band hand-held and low-power battery operated iso/iec 14443 type a read/writers reader to reader inductive/near field communications
3 4407a?scr?04/05 block diagram the host system, typically containing an application microprocessor, can control the operation of the AT90RF135602 by interfacing commands and application data over a bi-directional serial peripheral interconnect (spi) interface. figure 1. typical system architecture the partitioning of the system into its typical protocol layers is shown in figure 2. the exact boundary of each layer of the protocol stack is dependent on the specific application and, therefore, the optimal architectural split of the protocol layers. software implementation of the protocol stack allows for operation with multiple parallel stacks as well as greater flexibility for customisation and future updates. micro controller rf reader passive low profile ball grid array (lbga) spi antenna coil host 13.56 mhz xtal regulator (2.8v)
4 4407a?scr?04/05 figure 2. overview of typical protocol layers based on osi 7-layermodel scan/read/write commands, etc. transmission protocol intialisation & anti-collision frame format & timing bit representation & timing modulation host micro application layer innovision r&t jewel ? mifare ? ultralight protocol iso14443 part 3 iso14443 part 3 iso14443 part 2 iso14443 part 2 reader micro reader asic
5 4407a?scr?04/05 pinout figure 3. lbga36 package pinout pin description pc4 sck miso (sdo) mosi (sdi) xtal2 vddq vcc2 vdd01 vdd02 gnd1 xin pc6 pc3 pc2 rx gnd2 /reset (/mclr) pc7 vcc1 xout tx1 vdd xtal1 pd1 substrate pc5 substrate vssq tx2 pdo pc1 pc0 fedcba 1 2 3 4 5 6 7 8 vss vss02 vss01 /ss table 1. at90rf15602 pin description pin name pin number i/0/p type description vddq f2 power analogue supply vdd e6 power logic supply vddo1 d2 power output stage supply vddo2 c2 power output stage supply vcc1 e3 power mcu supply vcc2 e2 power mcu supply gnd1 b2 power mcu gnd gnd2 b3 power mcu gnd vss b6 power logic gnd vssq b7 power analogue gnd vsso1 c7 power output stage gnd vsso2 d7 power output stage gnd
6 4407a?scr?04/05 substrate 1 f7 power gnd substrate 2 e7 power gnd /ss b1 input spi slave select (active low) * mosi (sdi) c1 input spi data input * miso (sdo) d1 output spi data output * sck e1 input spi clock * /reset (/mclr) a3 input reset (active low) pd0 f8 reserved pd1 f6 reserved pc0 a8 reserved pc1 b8 reserved pc2 d8 reserved pc3 e8 reserved pc4 f1 reserved pc5 a6 reserved pc6 f3 reserved pc7 f4 reserved tx1 f5 output antenna drive 1 tx2 a7 output antenna drive 2 rx c8 input antenna receiver xin a2 input 13.56 mhz crystal or clk input xout a4 output 13.56 mhz crystal or n/c xtal1 a5 reserved xtal2 a1 reserved table 1. at90rf15602 pin description (continued) pin name pin number i/0/p type description
7 4407a?scr?04/05 definition of terms asic - application specific integrated circuit bist - built in self test crc - cyclic redundancy check csum - check sum etsi - european telecommunication standards institute fcc - federal communications commission fc - frequency of carrier fifo - first in first out fs - frequency of subcarrier gui - graphical user interface twi - two wires interface lbga - low-profile ball grid array otp - one time programmable pc - personal computer (ibm compatible) pcd - proximity coupling device pcb - printed circuit board picc - proximity integrated circuit card ram - random access memory spi - serial peripheral interconnect tba - to be advised tbc - to be confirmed uart - universal asynchronous receiver transmitter xtal - quartz crystal functional specification outline functional specifications the major determination of the functionality is the embedded software. the following specification is designated for the latest v2.7 software release. the AT90RF135602 is designed to achieve the following requirements: passive rfid reader operation in the unlicensed 13.56 mhz band read/write operation using iso/iec14443-2 type a modulation schemes at data com- munication rates of 106 kbit/s conform to the standard of iso/iec14443-3 type a as far as is required to operate with the mifare ultralight and the innovision r&t low-cost jewel rfid ics low voltage operation from a 2.7v supply low current operation with stand-by sleep mode interface electrically to the host system controller via an spi based interface and associ- ated digital control signals operates with minimal battery power consumption to optimise the battery life in both active and standby modes operation with innovision r&t low-cost, low power proprietary tag protocols
8 4407a?scr?04/05 reader to reader inductive near field communications capability using innovision r&t proprietary protocols in software transparent modes for direct software controlled modulation protocols for maximum flexibility general specifications multi-protocol rfid ic: ? iso/iec14443a parts 2 & 3 (frame format) ? user transparent operation with both the philips mifare ultralight and innovision r&t low-cost jewel tags operation:read/write number of bytes: ? ultralight: 48 user read/write bytes ? jewel: 96 user read/write bytes tag scan rate:variable by host carrier frequency:external 13.56 mhz crystal controlled carrier field drive level: ? four software adjustable carrier field drive and q levels determined by selection of output stage drive impedance: level1 ? 40 ? level2 ? 20 ? (default for v2.7) level3 ? 10 ? level4 ? 5 ? antenna configuration:balanced ?push-pull? output stages driving a symmetrical series resonant antenna coil for optimal carrier field generation when operating from low voltage supply fcc/etsi emc compliancy:simple lc low-pass filters used on output stages to achieve harmonic reduction required for emc compliancy operating voltage range: 2.7 ? 3.0 v maximum voltage rating: 3.3 v peak supply current: < 65 ma peak (depending on drive level selection, antenna matching and tuning) sleep-mode quiescent current: <10 a (1 a typical) protocol control: atmel pre-programmed risc microprocessor software program memory: pre-programmed with innovision firmware revision v2.7 data memory: reserved non-volatile memory: reserved interfaces: ? 3 wire spi interface at 115 kbaud
9 4407a?scr?04/05 figure 4. recommended circuit for extended range
10 4407a?scr?04/05 figure 5. recommended circuit for short range application
11 4407a?scr?04/05 spi interface protocol serial peripheral interface ? spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the AT90RF135602 and peripheral devices or between several avr devices. the AT90RF135602 spi includes the following features: features full-duplex, three-wire synchronous data transfer master or slave operation lsb first or msb first data transfer seven programmable bit rates end of transmission interrupt flag write collision flag protection wake-up from idle mode double speed (ck/2) master spi mode figure 6. spi block diagram spi2x spi2x divider /2/4/8/16/32/64/128 clk io
12 4407a?scr?04/05 the interconnection between master and slave cpus with spi is shown in figure 7. the system consists of two shift registers, and a master clock generator. the spi mas- ter initiates the communication cycle when pulling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to inter- change data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the spi clock gener- ator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 7. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. shift enable
13 4407a?scr?04/05 general this section describes the operation and in terface protocol between the typical host controller and the AT90RF135602 for v2.7 of software. the AT90RF135602 always operates as a slave to the host controller device acting as the master. the spi interface operation is specified by the /ss and /reset lines as shown in the table below. to clarify: the AT90RF135602 ignores sck from the host and tri-states the mosi and miso lines whilst /ss is high as the slave, the AT90RF135602 accepts the sck from the host and produces serial output data from its miso output only when /ss is low. the mosi input is used to receive commands and data from the host in conjunction with the sck clock when /ss is low. operation from a cold power-up and reset defaults to be in low quiescent current ?sleep mode? waiting for /ss to go low. spi setup AT90RF135602 is slave. /ss idle condition is high. prior to transmitting a message the /ss line is set low by the host, after the message has been transmitted the /ss line is set back high again. the interval between the host lowering /ss and then generating the first sck pulse should be a minimum of 3us. sck idle condition is low. the leading edge is rising and the trailing edge falling. in each direction data is loaded on the rising clock edge and is valid (and sampled) on the falling clock edge. the minimum interval between the 8 th sck of a byte and the 1 st sck of the next byte shall be 10us for status poll commands and 23us for all other commands. spi command/response message structure the host generates the spi clock signals to send ?command? messages to the AT90RF135602. the host generates the spi clock signals to receive ?response? messages from the AT90RF135602. the generic message structure is independent of message direction and is transparent to the spi hardware interface. /reset /ss interface mode low low or high reserved high high sleep mode high low spi interface and AT90RF135602 active
14 4407a?scr?04/05 messages are either single byte or multi-byte. all messages are terminated by an 8-bit chec ksum byte (csum) this is calculated as the 8-bit sum of all the proceeding bytes in the message. multi-byte messages are indicated by the most significant bit set to ?1? in the first byte of the message. the length of the additional information is determined by the message type and nature of the additional information bytes. the maximum allowable length of a message including its checksum is 255 bytes. the host may command read/write to the whole of a tag or can restrict the operation to individual pages and sectors using a common message structure which can be indepen- dent of tag type. addressing modes the v2.7 AT90RF135602 software provides for two modes of addressing tags using either logical or physical addressing depending on the command variant. for logical addressing the application can work independent of tag type as long as the data capacity is not exceeded. the AT90RF135602 software will seamlessly handle the mapping of logical addresses over to either the innovision jewel or the philips mifare ultralight depending on the type of tag it recognises as being present. the mapping for logical start address is given in appendix a. for physical addressing the application layer must first know which type of tag is present and then address the memory bytes using physical addresses from the tag datasheet. the user is referred to relevant datasheet documentation. AT90RF135602 command message structure to wake-up the AT90RF135602 and to start the tag read or write operations the host as the master must send either a single or a multi-byte command message. the single byte message consists of a command byte and checksum byte, as follows: to AT90RF135602 = spi message type byte description single byte message (1 byte + checksum) 1 st byte 0x00 ? 0x7f single byte message type 2 nd byte csum multi-byte message (minimum of 3 bytes + checksum) 1 st byte 0x80 ? 0xff multi-byte message type 2 nd byte information byte 3 rd byte information byte 0 ? 251 bytes additional information bytes last byte csum
15 4407a?scr?04/05 the multi-byte message consists of a command byte, start address byte, data length value byte, the data (if relevant to the command) and checksum byte as follows: to AT90RF135602 = ?.. where: - is the command byte with top bit set (e.g. read, write, etc) - is the start address byte (0 to 255) for the operation* - is the length in number of bytes to read or write (0 to 240) - is data byte(s) - sent least significant byte first - if relevant to the command (e.g. for writing) ? is the 8-bit sum of the proceeding bytes the message is sent most significant byte (i.e. byte) first. the data bytes are sent least significant byte first. the 8-bit bytes are sent most significant bit first. subsequent to a command message (which both wakes-up the AT90RF135602 and starts the tag read or write operations) the host as the master should poll periodically to assess the status and progress of the commanded operation. * start address is given in logical terms for user read/write area (see appendix a) table of commands explanation bytes 0x00 poll status from AT90RF135602 = 0x00 = 0x00 0x70 built-in self test (see built-in self test section for further details) = 0x70 = 0x00 0x80 read user data logical (read requested number of us er r/w data bytes from requested logical start address of any tag type) = 0x80 = start logical address = number of bytes to be read = checksum user data starts at logical address 0x00 0x86 read physical (read requested number of byte s from requested physical start address of known tag type) nb application must know tag type = 0x86 = start physical address = number of bytes to be read = checksum 0x90 read uid/lock/otp/user data logical (read requested number of uid, lock, otp & user data bytes from requested logical start address of any tag type) = 0x90 = start logical address = number of bytes to be read = checksum uid starts at logical address 0x00 to 0x07 lock bits start at logical address 0x08 to 0x09 otp bits start at logical address 0x0a to 0x0f user data starts at logical address 0x10
16 4407a?scr?04/05 0xa0 write user data logical (write requested number of us er data bytes starting at requested logical address of any tag type) = 0xa0 = start logical address = number of bytes to write (n) ? = n bytes to write = checksum user data starts at logical address 0x00 0xa4 write user data logical to specific uid (verify specific uid; if equal then write requested number of data bytes starting at requested logical address and verify, if still present) = 0xa4 = start logical address = number of bytes to write (n) ? = uid of specified tag ? = n bytes to write = checksum user data starts at logical address 0x00 0xa6 write physical (write requested number of bytes starting at requested physical address of known tag type and verify, if still present) nb: application must know tag type = 0xa6 = start physical address = number of bytes to write (n) ? = n bytes to write = checksum 0xa8 write physical to specific uid (verify specific uid; if equal then write requested number of bytes starting at requested physical address of known tag type and verify, if still present) nb: application must know tag type = 0xa8 = start physical address = number of bytes to write (n) ? = uid of specified tag ? = n bytes to write = checksum user data starts at logical address 0x00 0xac reader ic configuration diagnostic command configuration data ? 3 bytes 0xac010020 ? selects 40 ? driver resistance 0xac030020 ? selects 20 ? driver resistance 0xac050020 ? selects 10 ? driver resistance 0xac070020 ? selects 5 ? driver resistance this setting remains in force for subsequent communications with the tag until the AT90RF135602 is reset. the default driver resistance a fter reset or power up is 20 ? for software v2.7. 0xb0 write lock/otp/user data logical (write requested number of lock, otp & user data bytes to requested logical start address of any tag type and verify, if still present) nb: writing to uid area is not valid = 0xb0 = start logical address = number of bytes to write(n) ? = n bytes to write = checksum uid starts at logical address 0x00 to 0x07 lock bits start at logical address 0x08 to 0x09 otp bits start at logical address 0x0a to 0x0f user data starts at logical address 0x10 explanation bytes
17 4407a?scr?04/05 see appendix b for an example command response sequence. AT90RF135602 response message structure at the same time as the host sends a message, the AT90RF135602 returns its status response: single byte response from AT90RF135602 = if the AT90RF135602 is still busy processing the last command then the response data received during the 16 clock periods of the polling command message will be: status = 0x01 which means AT90RF135602 busy. when the AT90RF135602 has finished its operation, or has error conditions, then either a single byte or a multi-byte status message will be returned by spi clocks from the host. multi-byte response from AT90RF135602 = where: ? status response ? status byte 1 which includes further information (e.g. tag type from the previous operation) ? is the length in number of bytes that were successfully read or written (0 to 240). it is only present if relevant to the status response. - is data byte(s), if relevant to the command (e.g. for reading) ? is the 8-bit sum of the proceeding bytes the message is sent byte first. the data bytes are sent least significant byte first. the 8-bit bytes are sent most significant bit first. 0xb4 write lock/otp/user data logical to specific uid (verify specific uid of tag; if equal then write requested number of lock, otp & user data bytes to requested logical start address of any tag type and verify, if still present) nb: writing to uid area is not valid. = 0xb4 = start logical address = number of bytes to write(n) ? = uid of specified tag ? = n bytes to write = checksum uid starts at logical address 0x00 to 0x07 lock bits start at logical address 0x08 to 0x09 otp bits start at logical address 0x0a to 0x0f user data starts at logical address 0x10 explanation bytes
18 4407a?scr?04/05 table of responses the checksum byte is not shown in the table below. single byte responses multi-byte responses explanation bytes 0x00 normal operation = 0x00 = checksum 0x01 busy processing last command = 0x01 = checksum 0x10 spi command format error = 0x10 = checksum 0x20 no tag found = 0x20 = checksum explanation bytes 0x80 read user data logical successful = 0x80 = tag type = number bytes successfully read (n) ? = n bytes read = checksum user data starts at logical address 0x00 0x86 read user data physical successful = 0x86 = tag type = number bytes successfully read (n) ? = n bytes read = checksum 0x90 read uid/lock/otp/user data logical successful = 0x90 = tag type = number bytes successfully read (n) ? = n bytes read = checksum uid starts at logical address 0x00 to 0x07 lock bits start at logical address 0x08 to 0x09 otp bits start at logical address 0x0a to 0x0f user data starts at logical address 0x10 0x8f read error = 0x8f = error code: 1 byte = checksum 0xa0 write user data logical successful = 0xa0 = tag type = number bytes successfully written = checksum
19 4407a?scr?04/05 ta g ty p e error code see appendix b for an example command response sequence. 0xa4 write user data logical to specific uid successful = 0xa4 = tag type = number bytes successfully written = checksum 0xa6 write physical successful = 0xa6 = tag type = number bytes successfully written = checksum 0xa8 write physical to specific uid successful = 0xa8 = tag type = number bytes successfully written = checksum 0xb0 write lock/otp/user data logical successful = 0xb0 = tag type = number bytes successfully written = checksum 0xb4 write lock/otp/user data logical to specific uid successful = 0xb4 = tag type = number bytes successfully written = checksum 0xaf write error = 0xaf = error code: 1 byte = checksum 0xba built-in self test response (see built-in self test section for further details). = 0xba = test result ? = software version: 2 bytes serial number/production information: 8 bytes = checksum explanation bytes explanation 0x44 mifare ultralight 0x0c innovision jewel explanation 0x10 verify error during write 0x11 wrong serial number tag present for specific write 0x12 area to be written is locked 0x13 start address out of range 0x14 write size exceeds tag capacity
20 4407a?scr?04/05 sleep-mode the AT90RF135602 will enter low quiescent current ?sleep mode? when /ss is high and all tag operations have been completed. spi clock frequency this is determined by the host micro-controlle r, since this is the master and hence will generate the sck signal. the recommended spi clock frequency is 115khz. power on reset, reset & host in-circuit programming power on reset (por) from cold start the por will occur followed by initialisation of the microprocessor. from application of power the AT90RF135602 will be ready to receive an spi command data within 6 ms. reset the active low /reset signal from the host will cause the AT90RF135602 to enter the reset condition. from release of this signal high the AT90RF135602 will be ready to receive spi command data within 6 ms. when /reset is held low the AT90RF135602 will enter serial programming mode. in this mode the spi sck, miso, mosi lines may be used to upgrade the firmware. built-in self test (bist) mode general the bist consists of a single sequence of test stages designed as a confidence test that the AT90RF135602 is operational and also as a basic diagnostic aid if operation becomes impaired. beyond this it is not possible to perform an exhaustive test of operational performance without the presence of a tag for functional test purposes. initiation the bist mode is activated by the single byte host spi command 0x70. bist sequence: crc verification of all flash program memory if this test fails, subsequent tests are not performed. integrity of all ram memory if this test fails, subsequent tests are not performed. loop around test the loop around test is designed to test the xtal oscillator, antenna drive and demodu- lator sections of the at88rf135602 for connectivity and operation to a limited functional extent.
21 4407a?scr?04/05 bist response the bist response is composed of 12 bytes followed by a checksum. the structure of the response is shown in following table: an example of the bist response is shown below 0xba, 0x00, 0x02, 0x07, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 0xba: bist response 0x00: successful test result 0x02,0x07: software version 2.7 0x11,0x22,0x33,0x44: serial/production information 0x11223344 0x55,0x66,0x77,0x88: serial/production information 0x55667788 byte name description 1 built-in self test response 0xba 2 test result the test result byte indicates the progress of the self-test. test errors are indicated in a bit- wise fashion as listed below: 0x00 : all tests passed 0x01 : flash crc verification problem 0x02 : ram integrity problem 0x04 : loop back problem 3-4 ?. software version 2 byte (msb first) data representing the software version of the application in flash memory. for example 0x02, 0x07 represents version v2.7 5-12 ?. serial number and production information 8 bytes, (msb first), representing the serial number and production information stored in eeprom.
22 4407a?scr?04/05 appendix a ? tag memory maps a1 mapping between logi cal address & philips mifare ultralight physical memory logical address for user data only; 0x80 0xa0 0xa4 logical address for; 0x90 0xb0 0xb4 physical address description page byte number name comments - 0?2 0 0-2 sn0 ? sn2 serial number (uid) - 3?6 1 0-3 sn3 ? sn6 serial number (uid) -7 - - - - - 8-9 2 2-3 lock0-lock1 lock bytes - 10?13 3 0-3 otp0 ? otp3 otp ? writes are bit-wise ?or- ed? with existing contents - 14-15 - - - - 0-3 16-19 4 0 ? 3 data0 ? data3 user data area - read/write 4-7 20-23 5 0 ? 3 data4 ? data7 user data area - read/write 8-11 24-27 6 0 ? 3 data8 ? data11 user data area - read/write 12-15 28-31 7 0 ? 3 data12 ? data15 user data area - read/write 16-19 32-35 8 0 ? 3 data16 ? data19 user data area - read/write 20-23 36-39 9 0 ? 3 data20 ? data23 user data area - read/write 24-27 40-43 10 0 ? 3 data24 ? data27 user data area - read/write 28-31 44-47 11 0 ? 3 data28 ? data31 user data area - read/write 32?35 48?51 12 0 ? 3 data32 ? data35 user data area - read/write 36-39 52-55 13 0 ? 3 data36 ? data39 user data area - read/write 40-43 56-59 14 0 ? 3 data40 ? data43 user data area - read/write
23 4407a?scr?04/05 a2 mapping between logical address & innovision jewel physical memory logical address for user data only; 0x80 0xa0 0xa4 logical address for; 0x90 0xb0 0xb4 physical address description block (hex) byte number name comments - 0?7 0 0-7 uid0 ? uid7 unique identification number (used to verify correct tag is the target of read/write commands) - 8?9 e 0-1 lock0 ? lock1 lock bytes - 10-15 e 2-7 otp0 ? otp5 otp ? writes are bit-wise ?or-ed? with existing contents 0?7 16-23 1 0-7 data0 ? data7 user data area - read/write 8-15 24-31 2 0-7 data8 ? data15 user data area - read/write 16-23 32-39 3 0-7 data16 ? data23 user data area - read/write 24-31 40-47 4 0-7 data24 ? data31 user data area - read/write 32-39 48-55 5 0-7 data32 ? data39 user data area - read/write 40-47 56-63 6 0-7 data40 ? data47 user data area - read/write 48-55 64-71 7 0-7 data48 ? data55 user data area - read/write 56-63 72-79 8 0-7 data56 ? data63 user data area - read/write 64-71 80?87 9 0-7 data64 ? data71 user data area - read/write 72-79 88-95 a 0-7 data72 ? data79 user data area - read/write 80?87 96-103 b 0-7 data80 ? data87 user data area - read/write 88-95 104-111 c 0-7 data88 ? data95 user data area - read/write
24 4407a?scr?04/05 a3 lock bit functionality this section outlines the operation of the lock bits located at logical address 8 & 9 for commands 0x90, 0xb0, 0xb4. the lock bits are used to ?write protect? blocks of memory. for example, bit 0 of lock byte 0 locks the first 8 data bytes (addresses 0x10 to 0x17 for commands 0x90, 0xb0, 0xb4) bit 1 of lock byte 0 locks the second block of 8 data bytes (addresses 0x18 to 0x1f for commands 0x90, 0xb0, 0xb4) the correlation between lock bits and areas of logical memory locked is shown in the table below: lock byte 0 lock byte 1 memory locations locked (decimal) bit msb ? 7654321lsb - 0 0x80, 0x84, 0xa0, 0xa4 commands 56 ? 63* 48 ? 55* 40 ? 47 32 ? 39 24 ? 31 16 ? 23 08 ? 15 00 ? 07 0x90, 0xb0, 0xb4 commands 72 ? 79* 64 ? 71* 56 ? 63 48 ? 55 40 ? 47 32 ? 39 24 ? 31 16 ? 23 memory locations locked (decimal) bit msb ? 7654321lsb - 0 0x80, 0x84, 0xa0, 0xa4 commands unused unused unused unused 88 ? 95* 80 ? 87* 72 ? 79* 64 ? 71* 0x90, 0xb0, 0xb4 commands unused unused unused unused 104 ?111* 96 ? 103* 88 ? 95* 80 ? 87*
25 4407a?scr?04/05 appendix b ? command examples b1 command response sequence example 1 to read 3 bytes of data starting from logical address data4: command, = 0x80 start address, = 0x04 data length value, = 0x03 checksum, = 0x87 with tag present initiate read; c1: <80><04><03><87> r1: <00><00> poll status; c2: <00><00> r2: <01><01>AT90RF135602 is busy poll status; c3: <00><00> r3: <01><01>AT90RF135602 is busy poll status; c4: <00><00> r4: <80><44><03><44><55><66> read successful response = 0x80 tag type = 0x44 (mifare ultralight ) number of bytes successfully read = 0x03 data4=0x44, data5=0x55, data6=0x66 checksum = 0xc6 b2 command response sequence example 2 to read 3 bytes of data starting from logical address data4: command, = 0x80 start address, = 0x04 data length value, = 0x03 checksum, = 0x87 no tag present initiate read; c1: <80><04><03><87> r1: <00><00> poll status;
26 4407a?scr?04/05 c2: <00><00> r2: <01><01>AT90RF135602 is busy poll status; c3: <00><00> r3: <01><01>AT90RF135602 is busy poll status; c4: <00><00> r4: <20><20> no tag found status = 0x20 checksum = 0x20 b3 command response sequence example 3 to write 4 bytes of data, starting from logical address data5: command, = 0xa0. start address, = 0x05. data length value, = 0x04. data5 = 0x55, data6 = 0x66, data7 = 0x77, data8 = 0x88. checksum, = 0x63. with tag present initiate write; c1: <05><04><55><66><77><88><63> r1: <00><00> poll status; c2: <00><00> r2: <01><01>AT90RF135602 is busy poll status; c3: <00><00> r3: <01><01>AT90RF135602 is busy poll status; c4: <00><00> r4: <44><04> write successful response = 0xa0 tag type = 0x44 number of bytes successfully written = 0x04 checksum = 0xe8
27 4407a?scr?04/05 electrical characteristics absolute maximum ratings dc parameters i = industrial ........................................................-40 c to 85 c operating temperature................................... -30 c to + 80 c storagetemperature ....................................... -40 c to + 85 c voltage on v cc to v ss ......................................-0.5v to + 6.5v voltage on any pin to v ss ..........................-0.5v to v cc + 0.5v power dissipation typical........................................... 120 mw power dissipation max ............................................... 300 mw note: stresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. power dissipation is based on the maximum allow- able die temperature and the thermal resistance of the package. symbol parameter conditions min typ max unit i cc supply voltage 2.7 2.8 3.0 v i cc power down sleep mode current consumption 1ua 10ua a i cc active (field off) operating current 6.6 ma i cc active (field on) transmitting current max drive level 40 65 ma i ol/h output current at tx1 or tx2 -100 100 ma output resistance at tx1 or tx2 drive level 1 40 ? drive level 2 20 ? drive level 3 10 ? drive level 4 5 ? rise and fall time for 100% ask s xtal frequency range 13 13.56 14 mhz ext clock xin 1 vcc v (p-p) rx input resistance 8.8 11 13.2 k ? rx input capacitance 4 pf rx input delta carrier envelope change mv p-p rx input envelope amplitude 1 2v p-p v il input low voltage -0.5 0.3vcc v v ih input high voltage 0.6vcc vcc+0.5 v v ol output low voltage i ol =10ma vcc=2.7v 0.5 v v oh output high voltage i oh =-10ma vcc=2.7v 2.2 v
28 4407a?scr?04/05 ac parameters figure 8. power characteristics note: 1. sleep current is n~1ua with the pc3-xin link and ~36ua without the link, (operational mode set appropriately) o n 1.0 july 2004 30 line state waveform power vcc 2.8v 0v _____ reset high low slave select __ spi ss high low power consumption active :~6.7ma sleep - ~1ua* 1 2 3
29 4407a?scr?04/05 figure 9. spi characteristics line state waveform slave select /ss high low 9 4 8 clock sck high low 6 5 7
30 4407a?scr?04/05 figure 10. command execution characteristics line state waveform slave select /ss high low clock sck high low read tag read read command data transfer power consumption tag communication ? ~40ma host communication ? ~6.7ma sleep ~ 1ua 10 11 12
31 4407a?scr?04/05 note: 1. ?-? no value applicable 2. the AT90RF135602 will enter its power saving sleep mode when the /ss line is inactive (high) and any tag read/write oper- ation has been completed. 3. the AT90RF135602 will exit its sleep mode when /ss goes active (low). 4. the host should maintain /ss active only for the duration of the communication, this allows the AT90RF135602 to know when it is safe to enter sleep mode or when its spi transmission buffer may be updated. 5. the AT90RF135602 will tri-state the miso line when /ss is high. 6. the AT90RF135602 will enter serial programming mode if /reset is held low. table 2. interface timing parameters id description min ( s) typical max ( s) 1 AT90RF135602 cold power up time - 498 ms - 2 spi /ss low to exit from sleep mode (warm power up time) - 20 us - 3 spi /ss high to entry into sleep mode - 20 us - 4 spi /ss low to spi sck high 3 - - 5 spi sck period 3.2 - - 6 spi data rate poll : 40 non-poll : 50 -- 7 spi lsb to msb period poll : 10 non-poll : 23 -- 8 spi sck low to spi /ss high 6 - - 9 spi /ss high time 3-- 10 transmission of command 0x80 to read 16 bytes 0.8 ms 11 reading 16 bytes from mifare ultralight tag 8.0 ms 12 polling the response to the read 1.3 ms /ss high to miso tri-state - 10 ns - /ss low to miso output - 15 ns - _____ reset __ ss interface mode low - reserved high high spi interface sleeping miso tri-state high low spi interface active
32 4407a?scr?04/05 ordering information part number supply voltage (v) temperature range package packing green compliance AT90RF135602-7mtul 2.7 - 3.3 industrial lbga36 tray yes
33 4407a?scr?04/05 packaging information lbga 36 pin
34 4407a?scr?04/05
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products , other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions locate d on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implicati on. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4407a?scr?04/05 xm ? atmel corporation 2005. all rights reserved. atmel ? , logo and combinations thereof, avr?, and others, are registered trademarks, and everywhere y ou are sm and others are the trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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